Staff Digital ASIC Design Engineer

Headhunter: Intellectual Capital Resources

Semiconductor Production

Nederland

Senior Specialist / Project Manager

Remote

Experteer Overview

In this role you will own CPU architecture and subsystem integration for SoCs in the ultra-low-power AI hardware space. You’ll translate system requirements into CPU and subsystem specs and drive front-end RTL development. You’ll collaborate across SoC teams to ensure robust CPU operation and validation, enabling software-hardware co-design and IP integration. This is a hands-on position at the forefront of RISC-V CPUs, with impact on core performance and system integration.

Responsibilities

Design and architect RISC-V CPU cores and related micro-architectures
Translate system requirements into CPU/subsystem specifications
Develop, debug and maintain RTL in Verilog/SystemVerilog for CPU/related logic
Define SoC-level CPU integration including memory, interconnect and peripherals
Support top-level SoC validation with emphasis on CPU operation
Own front-end activities such as synthesis, STA and equivalence checking
Contribute to software-hardware co-design and CPU bring-up
Assess and integrate third-party CPU-related IP where appropriatee designs

Key requirements

Strong hands-on experience with CPU architecture and micro-architecture design
Practical experience with RISC-V based CPU cores, including customization or extension
Deep understanding of CPU pipelines, memory systems, caches, MMUs, interrupts and bus interfaces
Proven ability to write and debug complex RTL using Verilog/SystemVerilog
Solid knowledge of SoC architecture focusing on CPU integration
Experience across front-end design flows, including synthesis, STA and formal checking
Familiarity with on-chip interconnect protocols such as AXI or AHB
Ability to collaborate with verification teams and understand CPU-centric verification strategies

Cross-functional collaboration Communication with verification teams Problem-solving mindset RISC-V CPU core design Verilog/SystemVerilog RTL development Synthesis and static timing analysis (STA)

Description

In this role you will own CPU architecture and subsystem integration for SoCs in the ultra-low-power AI hardware space. You’ll translate sys…

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