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STA Engineer

Headhunter: Intellectual Capital Resources

Headhunter: Intellectual Capital Resources

Semiconductor Production

8040 Zürich, Zurich - Schweiz

Senior Specialist / Project Manager

Experteer Overview

As a Physical Design Engineer, you will own backend implementation challenges for advanced ASIC designs, focusing on timing-driven flows from RTL to GDSII. You’ll drive synthesis, STA, and timing closure to meet PPA targets, collaborating with digital, custom, and verification teams to enable successful tapeouts. This role offers the opportunity to shape backend methodologies within a growing silicon team and contribute to high-performance silicon products. You will work hands-on on critical challenges across complex IP and SoC subsystems, leveraging cutting-edge EDA toolchains.

Responsibilities

  • endorse and execute timing-driven physical implementation
  • perform synthesis and STA to achieve timing closure
  • drive MCMM implementation and sign-off
  • manage RTL-to-GDSII flow and ECOs
  • optimize power and sign-off processes
  • support tapeout execution and methodology development
  • collaborate with cross-functional teams (digital, custom, verification)
  • apply hierarchical design and clocking strategies

Key requirements

  • strong Physical Design / Backend ASIC implementation experience
  • expertise in Synthesis and STA
  • timing closure and MCMM sign-off
  • RTL-to-GDSII experience
  • proficiency with Synopsys or Cadence toolchains
  • experience with advanced process nodes and high-performance designs
  • UPF/CPF and low-power implementation knowledge
  • ECO implementation, power optimization, and sign-off flows
  • clocking strategies and hierarchical design understanding
  • scripting experience (Tcl, Python, or Shell)
  • strong debugging and problem-solving skills
  • ability to work with cross-functional teams

Description

As a Physical Design Engineer, you will own backend implementation challenges for advanced ASIC designs, focusing on timing-driven flows fro…
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